The present invention relates generally to three-dimensional (3D) memory devices and more particularly, to a 3D memory device having a multi-plane architecture.
The development of semiconductor memory devices is one characterized in part by continuous improvement in memory cell density (i.e., the number of memory cells provided per unit surface area). One approach to the fabrication of memory cells with higher memory cell integration density uses a vertically stacked arrangement of multiple substrate layers. The term “vertical” in this context is merely an orientation reference commonly drawn in relation to the principal planar surface of a base substrate. The result stack of memory devices or stack of substrates incorporating memory cell arrays may be termed a three-dimensional array structure, or 3-dimensional memory device.
Examples of conventional 3-dimensional memory devices may be found in U.S. Pat. No. 5,835,396 Nov. 10, 1998 and entitled “THREE-DIMENSIONAL READ-ONLY MEMORY”, U.S. Pat. No. 6,034,882 issued Mar. 7, 2000 and entitled, “VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION”, and U.S. Pat. No. 7,002,825 issued Feb. 21, 2006 and entitled, “WORD LINE ARRANGEMENT HAVING SEGMENTED WORD LINES”. The collective subject matter of these documents is hereby incorporated by reference.
As described in the foregoing reference documents, 3-dimensional memory devices typically include memory cell arrays formed in each layer of a vertical stacked plurality of semiconductor material layers. Most commonly, such semiconductor material layers are formed from silicon substrates using conventionally understood fabrication techniques. In certain examples, stacked layers may be formed using epitaxial growth processes.
However, since conventional 3D memory devices use a composite (or amalgamated) memory array implemented by a plurality of individual memory arrays arranged in a multi-plane structure, defined blocks of data (i.e., memory blocks) are distributed across a plurality of individual memory arrays disposed at different planes within the device. As a result, a single read, write, or erase operation directed to a particular memory block must be conducted in relation to different memory arrays in multiple planes.